With the ever-decreasing geometries in modern integrated circuits (ICs), the amount of charge used to represent a logic state has decreased to a level where single-events can now be a major reliability issue.
A single-event transient (SET) typically occurs when stray, high-energy particles or radiation (e.g., cosmic rays, protons, heavy ions, etc.) strike a sensitive node of a device, such as an integrated circuit. The strike may induce electron-hole pairs in the integrated circuit, which may in turn cause current spikes resulting in a SET in the integrated circuit.
Depending on the location of the strike, the SET may directly or indirectly result in faults that impair the normal operation of the integrated circuit. For example, in a combinational logic circuit, a SET occurring at an internal node of the circuit may cause a logic node to change state, possibly resulting in an incorrect output of the logic circuit.
Accordingly, faults occurring as a result of SET may result in significant errors at circuit output nodes and thus lead to system failures. Such failures can be especially severe in critical computational systems, such as in aerospace applications. Increased exposure to radiation, which is common in aerospace applications, only serves to compound this problem due to the increased prevalence of SETs from the radiation.
Soft error rates in ICs, including errors caused by SETs, are predicted to increase significantly if current technology scaling trends continue. Dual- or triple-redundancy hardening techniques are the most common approaches to mitigate SET pulses in combinational logic circuits. However, the area and power overhead required for such approaches can be too high for many applications.